Low-temperature poly-silicon (LTPS) thin-film transistors (TFTs) require high voltages for driving liquid crystal displays (LCDs) and electrophoretic displays, such as, for example, 8V-10V and 20-30V, respectively. High voltage operation is achieved by using relatively thick (e.g., >50 nm) gate dielectrics and drain-field relief structures, such as lightly doped drain (LDD) structures. Conventional source/drain and LDD structures require ion-implantation, which can be expensive. Additionally, activation of implanted doping requires high-temperatures or laser treatment. High temperatures necessitate using costly high-temperature glass carriers, and activation by laser treatment has controllability issues at high doping levels close to the solid solubility limit. Often, a combination of thermal annealing and laser treatment is used for activation, and overall the process can be expensive and complicated. In conventional LTPS TFT processes, at least two implantations followed by at least one activation step are needed to form n regions (LDD regions) and n++ regions (S/D regions).